STLD Lab
Experiment-1: Verification of functionality of logic gates
Various ICs used in Lab are:
NAND:
7400- 2 i/p - x4 gates
7410- 3 i/p - x3 gates
7420- 4 i/p - x2 gates
7430- 8 i/p - x1 gate
NOR:
7402-- 2 i/p - x4 gates
AND:
7408-- 2 i/p - x4 gates
7411-- 3 i/p - x3 gates
7421-- 4 i/p - x2 gates
OR:
7432-- 2 i/p - x4 gates
NOT:
7404-- - x6 gates
(a) OR gate:
Expression:
Y =A+B
Truth Table:
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
(b) AND gate:
Expression:
Y =A.B
Truth Table:
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
(c) NOT gate:
Expression:
Y =A'
Truth Table:
A Y
0 1
1 0
(d) NOR gate:
Expression:
Y =(A+B)' = A' . B'
Truth Table:
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
(e) NAND gate:
Expression:
Y = (A.B)' = A' + B'
Truth Table:
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
(f) ExOR gate:
Expression:
Y =A⨁B = A'B + AB'
Truth Table:
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
(g) ExNOR gate:
Expression:
Y = A⨀B = (A⨁B)' = A'B' + AB
Truth Table:
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Expreriment-2: Implement and Verify the functionality of a three variable minimal SOP.
A, B, C are inputs; Y is output.
Let the truth table be as shown.
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
Y = A'+BC'
Realize the above function using basic gates. The gates required here are:
NOT gate =2
OR gate =1
AND gate =1
Now verify the truth table inputs and outputs for the logic connections given in the kit.